Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies

Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a given size. The edges are used to generate fault critical areas. These are critical areas that are classified by the list of circuit nodes that are shorted by a defect of the given size falling within that area. Fault critical areas generated for a range of defect sizes can be used to produce fault probabilities between individual circuit nodes and enable device test procedures and redundancy strategies to be optimised. The algorithms have the advantage that they are not restricted to Manhatten layout and that they are computationally efficient. 1: Introduction The need for efficient critical area calculation is growing ever more important as the integrated circuit designer becomes increasingly interested in the yield of the final product. The critical area [1] is defined as the region of the circuit layout in which the centre of a circular defect has to fall in order to generate a circuit fault. Critical area calculations are already being used to explore the benefits of various design options [2, 3]. The division and classification of the critical area into separate regions that represent unique faults (shorts between circuit nodes) can by used to produce a gradedfault probability list. The set of possible faults for a given defect size is defined by the classified regions [4]. The probability of each fault can be estimated from the area of this region. Using the fault probability information a set of tests that exercise the identified faults can be generated and, by testing for the most probable faults first, the test time can be minimised [5, 6]. The use of such techniques to improve both the design and testing procedures for ICs can only become more important in an industry where profitability is the key to long term survival. Previously published work on yield prediction has been based on Monte Carlo methods [7], polygon operations [8] which are CPU intensive, or computionally efficient algorithms that are restricted to Manhatten layout [4, 5, 9]. These are of limited use in commercial layouts which are often large and will usually include non-Manhatten geometry. This paper presents two algorithms to generate and classify the edges that define critical areas. The algorithms are capable of handling arbitrary edges but the present implementation is restricted to angles that are multiples of 45 degrees. The results of these algorithms can be used to provide estimates of defect related yield loss and the probability of individual circuit faults. 1.1: Critical Area The critical area for extra material defects can be generated by bloating (by the radius of the defect) the polygons of the nodes that make up a circuit layer (e.g. , metal) and finding the regions where two or more polygons that belong to different nodes intersect, as illustrated in figure 1(a–d). The accuracy of the critical area measurements produced by the algorithms are dependant how well the bloat operation represents the expansion of the polygons by the defect radius. Greater accuracy can be obtained by “rounding off” the corners of polygons. (b) Bloated Polygons (c) Critical Area Generation (a) Polygons(Nodes) 1